What Arm announced
Arm launched the Neoverse CSS N4 compute subsystem on 8 September, part of a set of infrastructure announcements the company made the same day alongside an AI developer portal and a physical-AI partner programme.
CSS N4 supports between eight and 128 Neoverse N4 cores per die, built on TSMC’s N3P process and clocked at up to 3.8GHz. Arm says that at 128 cores running at 3GHz with 2MB of L2 cache per core, the subsystem delivers twice the socket performance of Neoverse N3, 1.25 times the performance per watt and 1.75 times the memory bandwidth.
Each configuration can carry up to 256MB of shared L3 cache, DDR5 or LPDDR6 memory, 128 lanes of PCIe 6 or 7, and CXL 4.0. It is the first N-series compute subsystem to support LPDDR6, and the first to reach PCIe Gen 7.
What a compute subsystem actually is
This matters more than the core count, and it is the part most easily lost. CSS N4 is not a processor Arm will sell. It is a pre-validated design framework that a customer configures — core count, cache size, memory controllers, I/O — and then takes to a foundry as its own chip.
That model is how Amazon’s Graviton family and Microsoft’s Azure Cobalt 100 were built, and it is why Arm’s share of the data centre has grown without Arm shipping a single server part itself. The hyperscalers wanted silicon tuned to their own workloads without designing a CPU core from scratch; CSS is the compromise that gets them there in a couple of years rather than five.
Why the memory and I/O matter more than the cores
For AI serving specifically, the two additions that count are LPDDR6 and PCIe Gen 7. Inference is memory-bound far more often than it is compute-bound: the accelerator sits waiting for weights and for key-value cache traffic, and the host CPU’s job is to keep data moving rather than to do arithmetic.
LPDDR6 raises bandwidth per watt, which matters in racks already limited by power rather than by space. PCIe Gen 7 doubles the link budget between host and accelerator, which is where a general-purpose CPU earns its place in an AI server at all. The 1.75x memory bandwidth figure is the one to hold on to; the 128 cores are the number that gets into headlines.
What to watch next
Named customers. A CSS generation is only real when someone announces a part built on it, and the interval between an Arm CSS launch and the first cloud silicon based on it has historically run to about two years. Watch the hyperscaler chip announcements in 2027 and 2028 for N4-derived parts, and watch whether anyone outside the big three takes it up.
